1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly relates to a scan path testing circuit built in a semiconductor integrated circuit device, and a delay fault testing method that uses the scan path testing circuit.
2. Description of the Related Art
In recent years, a larger scale and higher speed of a system LSI (Large Scale Integrated Circuit) has been advanced, and in association with the miniaturization of an LSI manufacturing process to support this advancement, a manufacture defect becomes more complex, which reveals an operational error of the LSI caused due to a delay fault. For this reason, the importance of a delay fault test in the system LSI becomes higher. As a method of attaining a circuit for the delay fault test, there are several methods, and the delay fault test that uses a scan path testing circuit is widely used.
As a fault model of a delay fault that are typically known and used, there are a transition delay fault model and a path delay fault model. In the transition delay fault, it is assumed that a delay time of one gate is elongated so that a fault is caused due to an input/output terminal of the gate. In the path delay fault, it is assumed that a delay time along one path is delayed, so that a fault is caused due to a path route itself. The transition delay fault model has a merit that a test having a high coverage is possible, and the path delay fault model has a merit that a test of a critical path having a high precision is possible. The generation of a test pattern corresponding to each of the fault models is made by using software based on an ATPG (Automatic Test Pattern Generation) technique.
Also, in an internal logic of the actual system LSI, there are timing exception paths which are referred to as a false path and a multi-cycle path that the necessity is not required that the delay time between flip-flops falls in one clock cycle. In the timing exception path, usually, the delay between the flip-flops after a layout design of a semiconductor chip does not actually fall in the one clock cycle. In the delay fault test, those timing exception paths are required to be removed at the time of the test.
The method of the delay fault test that uses a scan path circuit is disclosed in, for example, Japanese Laid Open Patent Application (JP-B-Showa, 52-28613). FIG. 1 shows a circuit diagram of a circuit when the delay fault test is performed in accordance with this conventional technique example. This delay fault testing circuit contains flip-flops 11 to 17 with a scan path test function, a combination circuit 10, NAND circuits 31 to 33 and a NOR circuit 34. Hereinafter, the flip-flops 11 to 17 with the scan path test function are also referred to as flip-flops 11 to 17.
In each of the flip-flops 11 to 17, a clock signal CLK is sent to a clock terminal CK, and a scan shift control signal SSC is sent to a scan shift control terminal SC. At the time of the scan path test, the flip-flops 11 to 17 form a scan path, and an output terminal Q in a former stage is connected to a scan-in terminal DT. That is, a scan-in signal SI is supplied to the scan-in terminal DT of the flip-flop 11 from outside, and the output terminal Q is connected to the scan-in terminal DT of the flip-flop 12 in a next stage. The output terminal Q of the flip-flop 12 is connected to the scan-in terminal DT of the flip-flop 13. The output terminal Q of the flip-flop 13 is connected to the scan-in terminal DT of the flip-flop 14. The output terminal Q of the flip-flop 14 is connected to the scan-in terminal DT of the flip-flop 15. The output terminal Q of the flip-flop 15 is connected to the scan-in terminal DT of the flip-flop 16. The output terminal Q of the flip-flop 16 is connected to the scan-in terminal DT of the flip-flop 17.
An input signal is sent from the combination circuit 10 to data input terminals D of the flip-flops 11, 12 and 14 to 16. The two input terminals of the NAND circuit 31 are connected to the output terminals Q of the flip-flops 11 and 12, and the output terminal of the NAND circuit 31 is connected to the data input terminal D of the flip-flop 13. The two input terminals of the NAND circuit 32 are connected to the output terminals Q of the flip-flops 13 and 14, and the output terminal of the NAND circuit 32 is connected to the input terminal of the NOR circuit 34. The two input terminals of the NAND circuit 33 are connected to the output terminals Q of the flip-flops 15 and 16, and the output terminal of the NAND circuit 33 is connected to the input terminal of the NOR circuit 34. The output terminal of the NOR circuit 34 is connected to the data input terminal D of the flip-flop 17. At the time of the scan path test, a scan-out signal SO is outputted from the output terminal Q of the flip-flop 17 to outside.
Each of the flip-flops 11 to 17 with the scan path test function contains a D-type flip-flop 101 and a selecting circuit 102, as shown in FIG. 13A. The selecting circuit 102 selects one of a signal supplied to a data input terminal D and a scan-in terminal DT in response to a signal supplied to a scan shift control terminal SC, and receives the selected signal to the D-type flip-flop 101. The D-type flip-flop 101 latches a data in synchronization with the rising edge of a clock signal supplied to the clock terminal CK. Thus, when the scan shift control terminal SC is in an “H” level, the signal level of the scan-in terminal DT is latched, and when it is at an “L” level, the signal level of the data input terminal D is latched.
Next, the operation of the circuit will be described below with reference to FIGS. 2A to 2J and FIGS. 3A to 3S. FIGS. 2A to 2J are timing charts showing the operation for setting a test data to the flip-flops 11 to 17. At a clock cycle C1, the scan shift control signal SSC is set to the “H” level (FIG. 2B), and a scan shift is started. At this time, the flip-flops 11 to 17 act as a shift register. Thus, the data set between the clock cycles C2 and C8 are sequentially sent to the flip-flops 11 to 17. In FIGS. 2A to 2J, the delay fault test for the path from the flip-flop 13 to the flip-flop 17 is assumed. The shift-in signal SI includes a serial data “LHHHLLL” (FIG. 2C), and the flip-flops 11 to 17 are set in “L”, “L”, “L”, “H”, “H”, “H” and “L”, respectively (FIGS. 2D to 2J).
After that, as shown in FIGS. 3A to 3S, the delay fault test is performed. In FIGS. 3A to 3S, a time axis is enlarged. A delay time td where the clock cycle C11 is defined is indicated. That is, it is checked that in synchronization with the rising edge of the clock cycle C11, the state of each flip-flop is changed and until of the rising edge of the clock cycle C12, a signal indicating a calculation result of the combination circuit arrives at each flip-flop. The time td of this clock cycle C11 is set to satisfy a desirable test standard (FIG. 3A).
At the clock cycle C9, since the flip-flops 11 to 17 output “L”, “L”, “L”, “H”, “H”, “H” and “L” from the output terminals Q, the output of the NAND circuit 31 is set to “H”, the output of the NAND circuit 32 is set to “H”, and the output of the NAND circuit 33 is set to “L” (FIGS. 3H, 3L and 3Q). The output of the NOR circuit 34 is in “L” (FIG. 3R). Here, the scan shift control signal SSC is set to “L”, and the flip-flops 11 to 17 are set to the states at which in synchronization with the clock signal CLK, the signals supplied to the data input terminals D are latched and held.
In the clock cycle C11, in synchronization with the rising edge of the clock signal CLK, the flip-flops 11 to 17 latches signals supplied to the data input terminals D. The flip-flop 11 latches “L” outputted from the combination circuit 10, and the flip-flops 12, 14 to 16 latches an “H” state outputted from the combination circuit 10. However, because of the same level as the clock cycle C9, the output signals are not changed. Since the NAND circuit 31 outputs the “H” level, the flip-flop 13 is changed from “L” to “H” (FIG. 3I). Thus, the output of the NAND circuit 32 is changed from “H” to “L” (FIG. 3L). When the output of the NAND circuit 32 becomes “L”, the NOR circuit 34 is changed to “H” because both of the inputs become “L” (FIG. 3R).
In the clock cycle C12, since the scan shift control signal SSC is in “L”, the flip-flops 11 to 17 latch the signal levels supplied to the data input terminals D. That is, the result of the delay fault test is latched by each flip-flop. The flip-flop 17 latches “H” outputted by the NOR circuit 34 and outputs it. Therefore, in the path from the flip-flop 13 to the flip-flop 17, the fact that the signal level in the period td of the clock cycle C11 is changed can be checked, and the satisfaction with the standard is known.
In the clock cycle C13, the scan shift control signal SSC becomes “H”. Then, the flip-flops 11 to 17 form a shift register and carry out the shifting operation. On and after the clock cycle C14, the states held in the flip-flops 11 to 17 are read out to an external terminal of the LSI, and the test result is determined.
In this way, the delay fault test is performed. However, for example, when the path from the flip-flop 13 to the NAND circuit 32 has a very long delay time, as indicated by the dotted lines in FIGS. 3A to 3S, the change in the output of the NAND circuit 32 is delayed (FIG. 3L), and the change in the output of the NOR circuit 34 is delayed (FIG. 3R). When a delay from a period td of the clock cycle C11 is present, the flip-flop 17 cannot latch the change in the output of the NOR circuit 34, and this results in an error in the delay fault test.
Usually, the delay of the path of the combination circuit portion in the circuit is required to fall in one clock cycle. However, in the case of the timing exception path where a timing restriction is relaxed, the delay is not restricted to one clock cycle. That is, the foregoing delay time td is not supplied to the timing exception path. When this route from the flip-flop 13 through the NAND circuit 32 and the NOR circuit 34 to the flip-flop 17 is the timing exception path, the signals of the timings indicated by the dotted lines in FIGS. 3A to 3S are observed in spite of the normal operations, and the delay faults are detected.
When the transition delay fault model is used to generate a test pattern for the delay fault test, the ATPG program generates a data to detect the delay fault of the NAND circuit 32, and the fact that the NAND circuit 32 is located on the route of the timing exception path is not recognized. For this reason, the test pattern through the timing exception path is generated, and the fault is detected in the delay fault test of the actual LSI. Thus, the LSI does not pass through the delay fault test.
For the generated test pattern, it is considered to perform a masking process in consideration of the influence of the timing exception path. However, in the test pattern of the large LSI, the individual study is not practical. Thus, in order to avoid this situation, when the ATPG program is executed, it is necessary to set a mask for the output of the flip-flop 17 serving as the final flip-flop of the timing exception path and then generate the test pattern. However, this mask setting is for the path arriving at the flip-flop 17. Consequently, the test result of the route from the flip-flop 16 through the NAND circuit 33 and the NOR circuit 34 to the flip-flop 17 is masked which is the non-timing exception path. Therefore, the delay fault detection of the usual path route where the timing exception path and the final flip-flop are same cannot be performed, which reduces a delay fault detection rate of the transition delay fault model.
As the method of the delay fault test in which the foregoing method is improved, a technique disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-219385) is known. FIG. 4 shows a circuit diagram of a delay fault testing circuit according to this conventional example. The circuit contains flip-flops 11, 12, 17, 18 and 23 to 26, a combination circuit 10, NAND circuits 31 to 33 and a NOR circuit 34. This circuit is approximately similar to the circuit shown in FIG. 1. However, the flip-flops 13 to 15 are replaced by the flip-flops 23 to 25 with the scan path test function having a normal signal selection holding function, and the flip-flop 16 is replaced by the flip-flop 26 with the scan path test function having an inversion signal holding function, and the flip-flop 18 is added.
In each of the flip-flops 11, 12, 23 to 26, 17 and 18, the clock signal CLK is sent to a clock terminal CK, and a scan shift control signal SSC is sent to a scan shift control terminal SC. At the time of the scan path test, these flip-flops form the scan path, and the output terminal Q in the former stage is connected to the scan-in terminal DT. That is, the scan-in signal SI is supplied to the scan-in terminal DT of the flip-flop 11 from outside, and the output terminal Q is connected to the scan-in terminal DT in the flip-flop 12 of the next stage. The output terminal Q of the flip-flop 12 is connected to the scan-in terminal DT of the flip-flop 23. The output terminal Q of the flip-flop 23 is connected to the scan-in terminal DT of the flip-flop 24. The output terminal Q of the flip-flop 24 is connected to the scan-in terminal DT of the flip-flop 25. The output terminal Q of the flip-flop 25 is connected to the scan-in terminal DT of the flip-flop 26. The output terminal Q of the flip-flop 26 is connected to the scan-in terminal DT of the flip-flop 17. The output terminal Q of the flip-flop 17 is connected to the scan-in terminal DT of the flip-flop 18.
An input signal is sent from the combination circuit 10 to the data input terminals D of the flip-flops 11, 12 and 24 to 26. The two input terminals of the NAND circuit 31 are connected to the output terminal Q of the flip-flop 11 and the output terminal Q of the flip-flop 12, and the output terminal of the NAND circuit 31 is connected to the data input terminal D of the flip-flop 23. The two input terminals of the NAND circuit 32 are connected to the output terminals Q of the flip-flops 23 and 24, and the output terminal of the NAND circuit 32 is connected to the input terminal of the NOR circuit 34. The two input terminals of the NAND circuit 33 are connected to the output terminals Q of the flip-flops 25 and 26, and the output terminal of the NAND circuit 33 is connected to the input terminal of the NOR circuit 34. The output terminal of the NOR circuit 34 is connected to the data input terminal D of the flip-flop 17. At the time of the scan path test, a scan-out signal SO is outputted from the output terminal Q of the flip-flop 17 to outside. The “L” level is always supplied to the data input terminal D of the flip-flop 18, and the output terminal Q is connected to normal signal selection holding control terminals HD of the flip-flops 23 to 25 and an inversion signal selection holding control terminal RV of the flip-flop 26.
As for the flip-flops 11, 12, 17 and 18, as explained above, FIG. 13A shows their internal configuration. Each of the flip-flops 23 to 25 with the scan path test function having the normal signal holding function contains a D-type flip-flop 111 and selecting circuits 112 and 113, as shown in FIG. 13B. The selecting circuit 113 selects one of a signal to be supplied to the scan-in terminal DT in response to a signal supplied to the normal signal selection holding control terminal HD, and the output signal of the D-type flip-flop and outputs to the selecting circuit 112. The selecting circuit 112 selects one of the signal to be supplied to the data input terminal D and an output signal of the selecting circuit 113 for outputting the test data response to the signal supplied to the scan shift control terminal SC, and outputs to the D-type flip-flop 111. The D-type flip-flop 111 latches the data in synchronization with the rising edge of the clock signal supplied to the clock terminal CK. Thus, in the flip-flop with the scan path test function having the normal signal holding function, when the scan shift control terminal SC is in the “L” level, the signal supplied to the data input terminal D is latched, and when the scan shift control terminal SC is in “H” and the normal signal selection holding control terminal HD is in “L”, the signal supplied to the scan-in terminal DT is latched. When the scan shift control terminal SC is in “H” and the normal signal selection holding control terminal HD is in “H”, the output signal of the D-type flip-flop 111 is latched in synchronization with the clock signal CK. That is, when the scan shift control terminal SC is in “H” and the normal signal selection holding control terminal HD is in “H”, the output of the flip-flop with the scan path test function having the normal signal holding function is not changed.
The flip-flop 26 with the scan path test function having the normal signal holding function contains a D-type flip-flop 121, selecting circuits 122, 123 and an inverter circuit 124, as shown in FIG. 13C. The selecting circuit 123 responses to the signal supplied to the inversion signal selection holding control terminal RV, selects any of the signal to be supplied to the scan-in terminal DT and the inversion signal of the output signal of the D-type flip-flop connected through the inverter circuit 124 and outputs to the selecting circuit 122. The selecting circuit 122 responses to the signal supplied to the scan shift control terminal SC, selects the signal supplied to the data input terminal D or the output signal of the selecting circuit 123 for outputting the test data and outputs to the D-type flip-flop 121. The D-type flip-flop 121 latches the data in synchronization with the rising edge of the clock signal supplied to the clock terminal CK. Thus, in the flip-flop with the scan path test function having the normal signal holding function, when the scan shift control terminal SC is at the “L” level, the signal supplied to the data input terminal D is latched, and when the scan shift control terminal SC is in “H” and the inversion signal selection holding control terminal RV is in “L”, the signal supplied to the scan-in terminal DT is latched, and when the scan shift control terminal SC is “H” and the inversion signal selection holding control terminal RV is in “H”, the inversion signal of the output signal of the D-type flip-flop 121 is latched, respectively, in synchronization with the clock signal CK. That is, when the scan shift control terminal SC is the “H” and the normal signal selection holding control terminal HD is in “H” and when the clock signal rises, the output of the flip-flop with the scan path test function having the inversion signal holding function is inverted.
The operation of the circuit will be described below with reference to FIGS. 5A to 5U. The operation for setting the test data for each flip-flop is the operation of the shift register as shown in FIG. 2. Thus, the detailed explanation is omitted. As shown in FIGS. 5A to 5U, the data set to carry out the delay fault test is “HHHHHLLH”. The scan-in signal SI gives “HLLHHHHH” in synchronization with the clock signal CLK in the period while the scan shift control signal SSC is in “H”. Thus, in the clock cycle C9, the flip-flops 11, 12, 23, 24, 25 and 18 hold the “H” level (FIGS. 5E, 5G, 5I, 5K, 5N and 5U), and the flip-flops 26, 17 hold the “L” level (FIGS. 5P, 5S).
The flip-flop 18 outputs “H” (FIG. 5U). Thus, in the clock cycle C11, even if the clock signal CLK rises, the respective outputs of the flip-flops 23 to 25 with the scan path test function having the normal signal holding function are not changed (FIGS. 5I, 5K and 5N). On the other hand, in the flip-flop 26 with the scan path test function having the inversion signal holding function, its output is inverted (FIG. 5P). That is, in accordance with the change in the output of the flip-flop 26 with the scan path test function having the inversion signal holding function, the delay fault test is performed. Even if the path from the flip-flop 23 to the flip-flop 17 is the timing exception path, the output of the flip-flop 23 is not changed. Therefore, this has no influence on the delay fault test.
In this way, in accordance with the route delay fault model, in order that the delay fault test of the route from the flip-flop 26 through the NAND circuit 33 and the NOR circuit 34 to the flip-flop 17 is made easier, the flip-flops 23 to 25 are replaced with the flip-flop with the scan path test function having the normal signal holding function, and the flip-flop 26 is replaced with the flip-flop with the scan path test function having the inversion signal holding function. For this reason, the route from the flip-flop 23 with the scan path test function having the normal signal holding function through the NAND circuit 32 and the NOR circuit 34 to the flip-flop 17 is not activated at the time of the delay fault test. Thus, when the test pattern is generated in accordance with the transition delay fault model, the mask setting is not required to be performed on the output of the flip-flop 17 in the ATPG program. However, the start flip-flop of the different route to the final flip-flop on the route targeted for the route delay fault test is replaced by the flip-flop with the holding function. Thus, the delay fault cannot be detected. In the case of the example in FIG. 4, the delay fault test cannot be performed on the route from the flip-flop 23 to the flip-flop 17, the route from the flip-flop 24 to the flip-flop 17 and the route from the flip-flop 25 to the flip-flop 17. Moreover, the flip-flop 23 is the flip-flop having the normal signal holding function at the time of the delay fault test. Thus, with regard to the route from the flip-flop 12 to the flip-flop 23 and the route from the flip-flop 11 to the flip-flop 23, the delay fault cannot be detected in accordance with the transition delay fault model. Therefore, even in this method, the delay fault detection rate based on the transition delay fault model is decreased.
As mentioned above, in the LSI in which the scale is made larger and the speed is made higher, it is important to increase the inclusion degree of the fault detection by using the delay fault test in which not only the route delay fault test for preferentially testing the critical path but also the transition delay fault test are combined. However, the conventional delay fault testing circuit could not attain this.